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RF is Radio Frequency, a signal with a very high frequency. The choice of circuit board substrate depends on the requirements for the performance indicators of the circuit board. It can be ordinary FR4 epoxy glass fiber or a special microwave substrate such as Teflon.
RF PCB standard：
- Low power RF PCBmainly uses standard FR4 material (good insulation properties, uniform material, dielectric constant ε=4, 10%).
- In the RF PCB design, each component should be closely arranged to ensure the shortest connection.
- For a mixed-signal PCB, the RF and analog partsshould be far away from the digital part (the distance is usually more than 2cm, at least 1cm), and the ground of the digital part should be separated from the RF part.
- When selecting components to work in a high-frequency environment, use SMD(Surface Mounted Devices) as much as possible. SMD are small in size, and the component pins are generally very short.
This article provides guidelines and suggestions for radio frequency (RF) printed circuit board (PCB) design and layout, including some discussion of mixed-signal applications, such as digital, analog, and RF components on the same PCB. The content is organized by topic areas and provides “best practice” guidelines, which should be applied in conjunction with all other design and manufacturing guidelines. These guidelines may also apply to specific components, PCB manufacturers, and materials.
Many of Maxim’s RF components require a transmission line with controlled impedance to transmit RF power to IC pins on the PCB. These transmission lines can be implemented on the outer layer (top or bottom layer) or buried in an inner layer. Guidelines for these transmission lines include discussions of microstrip lines, strip lines, coplanar waveguides (grounded), and characteristic impedance. It also introduces transmission line bending angle compensation and the layer change of the transmission line.
This transmission line includes a fixed-width metal trace (conductor) and a ground area located directly underneath (on the adjacent layer). For example, a microstrip on layer 1 (top metal) requires a solid ground area on layer 2 (Figure 1). The width of the trace, the thickness of the dielectric layer, and the dielectric determine the characteristic impedance (usually 50Ω or 75Ω)
This line includes a fixed-width trace on the inner layer and solid ground areas above and below.
The conductor can be located in the middle of the ground area (Figure 2) or have a certain offset (Figure 3). This method is suitable for the inner radiofrequency routing.
A coplanar waveguide provides better isolation between adjacent RF lines and other signal lines (end view). This medium includes an intermediate conductor and grounding areas on both sides and below (Figure 4).
Via “fences” are recommended on both sides of the coplanar waveguide, as shown in Figure 5. This top view provides an example of installing a row of ground vias in the top metal ground area on each side of the intermediate conductor. The loop currents induced on the top layer are shorted to the underlying ground plane.
Several calculation tools can properly set the signal conductor line width to achieve the target impedance. However, we should be careful when entering the dielectric constant of the circuit board layers.
The outer layer of typical PCBs contain less glass fiber than the inner layer, so the dielectric constant is lower. For example, the dielectric constant of FR4 material is generally εR = 4.2, while the outer substrate (prepreg) layer is generally εR = 3.8. The example below is for reference only. The metal thickness is 1oz copper (1.4 mils, 0.036mm).
When the transmission lines are required to be bent (change direction) due to wiring constraints, the bending radius used should be at least three times the width of the intermediate conductor. In other words:
Bending radius ≥ 3 × (line width).
This will minimize the characteristic impedance change of the corner.
If it is impossible to achieve gradual bending, the transmission line can be bent at right angles (non-curved), as shown in Figure 6. However, this must be compensated to reduce the sudden change in impedance caused by the increase in the local effective line width when passing through the bending point. The standard compensation method is the miter angle , as shown in the figure below. The formula of Douville and James gives the best microstrip right-angle miter:
In the formula, M is the ratio(%) of mitered and non-mitered corners. The formula is independent of the dielectric constant, and the constraint condition is w/h ≥ 0.25.
Similar methods can be used for other transmission lines. If there is any uncertainty about the correct compensation method, and the design requires a high-performance transmission line, we should use an electromagnetic simulator to model the bend.
Suppose the layout constraints require changing the transmission line to a different circuit board layer. In that case, it is recommended to use at least two vias for each transmission line to minimize the inductive loading. A pair of vias will effectively reduce the transmission inductance by 50%, and we should use the largest diameter via with the same width as the transmission line. For example, for a 15-mil microstrip line, the via diameter (finished plating diameter) should be 15 mil to 18 mil. If the space does not allow the use of large vias, we should use three transition vias with smaller diameters.
We must be careful to prevent accidental coupling between signal lines. The following are examples of potential coupling and preventive measures:
- RF transmission lines:The distance between the transmission lines should be as large as possible and should not be close to each other over a long distance. The smaller the distance between each other and the longer the distance between parallel traces, the greater the coupling between parallel microstrip lines. The traces on different layers should have ground areas to keep them separate. Transmission lines carrying high power should be as far away from other transmission lines as possible. Grounded coplanar waveguides provide excellent line-to-line isolation. It is unrealistic for the isolation better than -45dB between RF lines on a small PCB.
- High-speed digital signal lines:These signal lines should be arranged independently on a different circuit board layer from the RF signal lines to prevent coupling. Digital noise (from clocks, PLLs, etc.) will be coupled to the RF signal line and then modulated to the radio frequency carrier. In some cases, digital noise will be upconverted or
- VCC/power lines:These lines should be arranged on a dedicated layer. Appropriate decoupling or bypass capacitors should be installed at the main VCC distribution node and VCC branch. The bypass capacitor must be selected based on the overall frequency response of the RF IC and the expected frequency distribution of digital noise caused by the clock and PLL. These traces should also be kept isolated from the RF lines. Otherwise, they will emit larger RF power.
If layer 1 is used for radio frequency components and transmission lines, it is recommended to use a solid (continuous) ground area on layer 2. For strip lines and offset strip lines, the upper and lower intermediate conductors require grounding areas. These areas must not be shared or allocated to signal or power networks but must be allocated to the ground. Sometimes limited by design conditions, a local ground area on a specific layer must be located under all radio frequency components and transmission lines. The ground area must not be disconnected under the transmission line.
A large number of ground vias should be placed between different layers of the RF part of the PCB. This helps prevent ground current loops from increasing parasitic ground inductance. Vias also help prevent cross-coupling of RF signal lines and other signal lines on the PCB.
For the circuit board layers allocated to the system power (DC power) and ground, the loop current of the components must be considered. The general principle is to avoid placing signal lines on the circuit board layer between the power and ground layers.
If the component has multiple power connections, a common practice is to use power wiring in a “star” configuration (Figure 9). Install larger decoupling capacitors (tens of µF) at the “root” node of the star configuration, and install smaller capacitors on each branch. The value of these small capacitors depends on the operating frequency of the RF IC and its specific functions (i.e., decoupling between stages and the main power supply). An example is shown below:
Compared with the configuration in which all pins are connected to the same power network in series, the “star” configuration avoids long ground loops. Long ground loops will cause parasitic inductance, which can cause unexpected feedback loops. The key consideration for power supply decoupling is that the DC power supply must be electrically connected to an AC ground.
Due to the existence of self-resonant frequency (SRF), the capacitor’s effective frequency range, in reality, is limited. SRF can be obtained from the manufacturer, but sometimes must be characterized by direct measurement. Above SRF, the capacitor is inductive, so it has no decoupling or bypassing function. If broadband decoupling is required, the standard approach uses multiple (capacitance values) of increased capacitors, all in parallel. The SRF of a small capacitor is generally larger (for example, the SRF of a 0.2pF, 0402 SMT package capacitor = 14GHz). The SRF of a large capacitor is generally smaller (for example, the SRF of a 2pF capacitor in the same package = 4GHz). Table 2 lists typical configurations.
Since the power lines must be AC ground, it is essential to minimize the parasitic inductance of the AC ground loop. The component layout or placement direction may cause parasitic inductance, such as the ground direction of decoupling capacitors. There are two ways to place the bypass capacitor, as shown in Figure 10 and Figure 11:
In this configuration, connecting the VCC pad on the top layer to the via hole of the inner power supply region (layer) may hinder the AC ground current loop, forcing a longer loop, resulting in higher parasitic inductance. Any AC flowing into the VCC pin passes through the bypass capacitor, reaches its ground side, and then returns to the inner ground plane. In this configuration, the total footprint of the bypass capacitor and related vias is the smallest. In another configuration, the AC ground loop is not restricted by the vias in the power supply area. Generally speaking, this configuration requires a slightly larger PCB area.
Grounding of crowbar-connected components: For crowbar-connected (grounded) components such as power supply decoupling capacitors, it is recommended to use at least two ground vias for each component (Figure 12), reducing the influence of via parasitic inductance. The short-circuit connection component group can use via grounding “island.”
Most ICs require a solid ground area on the component layer (the top or bottom layer of the PCB) directly below the component. This ground area will carry DC and RF return flow through the PCB to the distributed ground area. The second function of the component “ground pad” is to provide a heat sink, so the pad should include the maximum number of vias as permitted by the PCB design rules.
In the example shown in the figure below, a 5 × 5 via array is installed in the middle ground area (on the component layer) directly below the RF IC (Figure 13). Where other layout considerations allow, the maximum number of vias should be used. These vias are ideal vias (through the entire PCB). These vias must be plated. If possible, use the thermal paste to fill the vias to improve heat dissipation (fill the thermal paste after plating the vias before finally plating the circuit board).
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